Inside the BSA Processing Element

Watch the actual hardware datapath compute w × x with zero multipliers. Each cycle: load a coefficient term → barrel-shift the input → add to accumulator. That's it.

Press ⚡ to watch the BSA PE compute a multiplication using only shifts and adds
Weight (w)
—
×
Input (x)
—
=
BSA Result
—
Weight decomposition: w = Σ s_r · 2^{e_r}
① Coefficient SRAM — Load term (s_r, e_r)
Sign (s_r)
—
Exponent (e_r)
—
Term value
—
↓ term loaded
② Barrel Shifter — x << e_r (single cycle)
Input x
= ?
↓ shifted value
③ Integer Adder — accumulator ±= shifted value
ACC
+
?
=
?
↓ new accumulator value
④ Accumulator Register — running total
0
decimal
BSA result:—
True w×x:—
Match:✓
—
BSA Cycles (shifts + adds)
—
MAC Cycles (multiply)

This is the entire compute pipeline. No multiplier. No floating-point unit. Every MAC in an LLM, a filter, a beamformer, a radar — all of it reduces to this: load a tuple, shift, add, repeat. The barrel shifter is ~500 gates. The accumulator is ~290 gates. Total PE: ~1,095 gates vs ~3,200 for an FP32 MAC — ~3× smaller, enabling ~3× more PEs per mm² of silicon.