RRAM Compute-In-Memory — BSA Binary Crossbar

Every prior CIM attempt requires multi-level cell discrimination — 8 to 16 resistance levels per cell. Noisy, temperature-sensitive, unreliable. BSA solves this: each RRAM cell stores one bit. High resistance or low resistance. ON or OFF. The computation happens in the memory itself.

Press ⚡ to watch BSA CIM compute a 4-element dot product in the RRAM crossbar

🔥 Analog CIM (Prior Art) — The Multi-Level Problem

Level 0
Level 4
Level 7
Drifted ⚠
Conductance levels8–16 per cell
Array yield60–80%
Conductance driftCritical failure
Temperature sensitivityHigh
Write endurance10³–10⁶ cycles

⚡ BSA Binary CIM — ON or OFF

ON (1)
OFF (0)
Conductance levels2 (binary)
Array yield>95%
Conductance driftNegligible
Temperature sensitivityLow
Write endurance10⁶–10¹² cycles
Live Crossbar — R=2 Stacked Binary Array with Shift-by-Wiring
Inputs (x)
x₀ = 3
x₁ = 5
x₂ = 2
x₃ = 7
Array 1 — Term 1 (2^e₁)
both arrays
receive same
input x
⟷
Array 2 — Term 2 (2^e₂)
Sense Lines
I₀
I₁
I₂
I₃
↓ Shift-by-Wiring: Array 1 output connects at bit position e₁, Array 2 at bit position e₂ ↓
No barrel shifter circuit needed — the shift is the wiring topology itself
Digital
Accumulator
0
0
0
0
0
0
0
0
2⁷
2⁶
2⁵
2⁴
2³
2²
2¹
2⁰
Result
—
🔌
Zero Data Movement
Weights live in RRAM. Computation happens where the data is stored. No memory bus, no bandwidth wall, no HBM.
🔀
Shift-by-Wiring
The power-of-two shift is just wire routing — connecting output bit-lines to the correct accumulator positions. Near-zero energy.
⚡
KCL Dot Product
Kirchhoff's Current Law sums currents along sense lines — computing the dot product in the physics, not in logic gates.
Why R=2? — The CIM Scaling Tradeoff

"Can you just use R=8 for higher precision?"

Technically yes. Practically no — and you don't need to. Here's why.

System Yield vs Number of Stacked Arrays
R (Arrays) Area System Yield Weight Coverage Verdict
R=1 1× 95.0% ~55% Coarse
R=2 2× 90.25% ~85% ★ Sweet Spot
R=4 4× 81.5% ~98% Diminishing
R=8 8× 66.3% ~99.5% Impractical
Yield = 0.95^R per array stack. At R=8, a third of crossbar stacks are defective — erasing the binary reliability advantage.
🟢 R=2 CIM
85% of weights
In-memory compute
Zero data movement
+
⚡ Digital PE
15% of weights
Higher R as needed
Dynamic-R adaptive
The optimal architecture is a hybrid. Post-QAT, 85% of weights are near exact powers of two and need only R≤2 terms. These stay in RRAM — zero data movement, maximum yield, binary reliability. The remaining 15% that need higher precision are routed to a small digital BSA PE. You don't build R=8 in CIM — you let the digital side handle the exceptions.

Every prior CIM attempt failed because analog MAC requires 8–16 resistance levels per cell.
BSA's binary decomposition needs only 2 levels — ON or OFF — RRAM's most reliable mode.

57–92× arithmetic energy reduction

The only active digital circuit is an integer adder tree.
No multiplier. No barrel shifter. No FP unit. Just wires and an adder.
95%+ array yield vs 60–80% for analog CIM. Fabricable at 22nm FDX.