Compilation Pipeline
STAGE 1
Python API
import abax
from abax.models import TransformerBlock
model = TransformerBlock(d_model=256, n_heads=4)
abax.device('soroban:edge')
result = model.forward(input_tensor)
Key: Same API for all domains — AI, 5G, DSP. One import, one device target.
STAGE 2
SLIDE Compiler
Graph optimization, operator fusion, memory planning
Key: Identifies MAC patterns, fuses operators, prepares weights for decomposition.
STAGE 3
Greedy Decomposition
w ≈ Σ sᵢ × 2eᵢ · mean R̄ = 1.6
0.7832
→
+2⁰
−2⁻²
+2⁻⁵
(R=3)
Key: Every weight becomes compact signed power-of-two terms.
STAGE 4
Coefficient Tables
Key: Entire model stored as compact integer tables — signs and shift amounts only.
STAGE 5
Hardware Execution
SRAM
→
Barrel Shifter
→
Adder
→
Accumulator
Key: Pure shift-and-add — no multiplier, no FPU. ~92× more energy-efficient.
Domain Comparison
Python API
model = TransformerBlock(d_model=256)
Neural network graph defined
Neural network graph defined
↓
SLIDE Compiler
Fuses MatMul+Add+ReLU layers
Identifies weight tensors W ∈ ℝd×d
Identifies weight tensors W ∈ ℝd×d
↓
Greedy Decomposition
Neural weights → PoT coefficients
wij → Σ sr · 2er, mean R̄ ≈ 1.6
wij → Σ sr · 2er, mean R̄ ≈ 1.6
↓
Coefficient Tables
Weight matrices → (sign, exponent) SRAM
INT4 storage, ~8× compression vs FP32
INT4 storage, ~8× compression vs FP32
↓
Hardware Execution
BSA PE array: shift activations by er
Accumulate across R terms per weight
Accumulate across R terms per weight
AI Inference: The most natural fit. QAT-trained models compress to R̄≈1.6 terms per weight. The PE array processes entire transformer layers with 2D sparsity yielding ~92× energy efficiency vs FP32 MAC (Horowitz 45nm).
Python API
beam = abax.beamform.SteeringVector(M=64)
Antenna array configuration defined
Antenna array configuration defined
↓
SLIDE Compiler
Maps complex matrix-vector products
Steering vectors W ∈ ℂM×R
Steering vectors W ∈ ℂM×R
↓
Greedy Decomposition
Steering vectors → PoT coefficients
Re(w) + j·Im(w), each decomposed separately
Re(w) + j·Im(w), each decomposed separately
↓
Coefficient Tables
Phase/magnitude → (sign, exponent) pairs
Updated per beam-sweep at sub-ms latency
Updated per beam-sweep at sub-ms latency
↓
Hardware Execution
Same BSA PE array — identical silicon
Shift-add computes beam weights in real-time
Shift-add computes beam weights in real-time
5G Beamforming: Steering vectors are naturally sparse in the PoT domain. The same PE array that runs AI inference computes beam weights at sub-millisecond latency — no dedicated RF-DSP ASIC needed.
Python API
filt = abax.dsp.FIRFilter(taps=128, fs=48000)
Filter specification defined
Filter specification defined
↓
SLIDE Compiler
Maps convolution to MAC operations
FIR taps h[n] identified as coefficients
FIR taps h[n] identified as coefficients
↓
Greedy Decomposition
FIR taps h[n] → PoT coefficients
Symmetric taps yield shared decompositions
Symmetric taps yield shared decompositions
↓
Coefficient Tables
Filter taps → (sign, exponent) SRAM
Hot-swappable: change filter = change table
Hot-swappable: change filter = change table
↓
Hardware Execution
Same BSA PE array — identical silicon
Streaming convolution via shift-and-add
Streaming convolution via shift-and-add
DSP Filtering: Classical FIR/IIR taps decompose cleanly into PoT terms. A 128-tap filter runs on the same PE array as a transformer — swap the coefficient table, not the silicon. Real-time audio at µW power.